Dr Prakash S P - Bannari Amman Institute of Technology

Experience Type	Organization	From	To	Total Experience
Engineering	Bannari Amman Institute of Technology, Sathyamangalam	01.06.2007

Degree	Specialization	Institute	University	Year of Passing
B.E	Electronics and Instrumentation	Kongu Engineering College	Bharathiar University, Coimbatore	2004
M.E	Applied Electronics	Bannari Amman Instituite of Technology	Bharathiar University, Coimbatore	2007
Ph.D	Information and Communication Engineering	Bannari Amman Instituite of Technology	Anna University, Chennai	2020

S.No.	Subject Area
1	Low Power VLSI
2	VLSI Signal Processing

Purushothaman V, Sivasamy J, Karthik S, Choubey A, Prakash S. P and Sheeba T. B, (2023). “Fuzzy C-Means Clustering Based Energy-Efficient Protected Optimal Path-Routing Protocol for MANET”, International Journal of Intelligent Systems and Applications in Engineering, 12(2s), 453–466. Retrieved from https://ijisae.org/index.php/IJISAE/article/view/3645

Prakash S P, S Tamilselvan, M Abdullah and R Ramesh, “Iot Based Solid Waste Management System Using Smart Dustbins”, IOP Conference Series: Earth and Environmental Science Purpose-led Publishing, find out more. PAPER • THE FOLLOWING ARTICLE ISOPEN ACCESS.

S. P. Prakash, N. R. Kumar, J. Vinu, K. Mohanasharan and M. Saabareesh, “Hybridization Methodology for Predicting ORE from Mines to End User using Machine Learning Technique,” 2023 Third International Conference on Smart Technologies, Communication and Robotics (STCR), Sathyamangalam, India, 2023, pp. 1-6, doi: 10.1109/STCR59085.2023.10396891.

K. R. N. Aswini, S. P. Prakash, G. Ravindran, T. Jagadesh and A. V. Naik, “An Extended Canberra Similarity Measure Method for Content-Based Image Retrieval,” 2023 International Conference on Evolutionary Algorithms and Soft Computing Techniques (EASCT), Bengaluru, India, 2023, pp. 1-5, doi: 10.1109/EASCT59475.2023.10392995.

M Abdullah, Prakash S P, K Beshir, A Ftsum Berhe and Y Petros Abo, “Hybrid Frequency Domain based Feature Extraction methods for Human Face Recognition,” 2022 Smart Technologies, Communication and Robotics (STCR), Sathyamangalam, India, 2022, pp. 1-5, doi: 10.1109/STCR55312.2022.10009385.

PRAKASH S P , IMPROVED LOCAL VECTOR PATTERN DESCRIPTOR FOR FACE RECOGNITION , Smart Technologies, Communication and Robotics , Vol. , Issue , pp 1 , 2023

M Abdullah, Prakash S P, K Beshir, A K Abebe and H H Takore, “Improved Local Vector Pattern Descriptor for Face Recognition,” 2022 Smart Technologies, Communication and Robotics (STCR), Sathyamangalam, India, 2022, pp. 1-5, doi: 10.1109/STCR55312.2022.10009318.

PRAKASH S P , IOT BASED SOLID WASTE MANAGEMENT SYSTEM USING SMART DUSTBINS , EARTH AND ENVIORNMENTAL SCIENCE , Vol.Vol. NO 1125 , IssueDEC2022 , pp 1 , 2022

L Pavithra, M Abdullah, SP Prakash, S Karthick, B Ragavi, VD Nandhini Wireless Sensor Networks: A Review on Sensor Deployment and Routing Protocols for Different Application IOP Conference Series: Materials Science and Engineering Vol. 1084, Issue 1, PP 012052, 2021

M.Abdullah,Dr.K.Premalatha,S.P.Prakash,S.Kirubakaran,Dr.S.Karthick Dr.C.Kamalanathan, “Improved Local Vector Pattern for Face Recognition”, International Conference on Design Innovation for 3CAS, IEEE, Bangalore, May 2019

S.Kirubakaran, S.Karthick, S.P.Prakash, “Increasing privacy for private database in cloud environment”, International Journal of Recent Technology and Engineering, Vol. 7, No. 4S, pp 394-397, JAN 2019.

S.P.Prakash, Dr.R.S.Valarmathy, Mr.M.Abdullah, Mr.S.Kirubakaran, “Noval approach in Face recognition using Hieratical Multi Scale Local Binary Pattern with ELM Classifier”, International Journal of Advanced Research in Science and Engineering, Vol. 6, No. 11, pp 2228-2232, NOV 2017.

S.P.Prakash, Dr.R.S.Valarmathy, M.Abdullah, S.Kirubakaran, “Noval approach in Face recognition using Hieratical Multi Scale Local Binary Pattern with ELM Classifier” International Conference on New Paradigms in Engineering Technology and Managemant -2017, Electronics Department, Pune, India., November 2017

S.P.Prakash , Dr.S.Valarmathy “An efficient utilization of adder for Multiple Constant Multiplier Architecture for FIR filter application “has been published in Journal of Computational and Theoretical Nanoscience American Scientific Publishers Vol. no 13 page no5093 – 5098 2017 ISSN 1546 – 1955. Annexture I 2016

S.P.Prakash, Dr.S.Valarmathy, The paper titled “Constant Multiplier Architecture For Reconfigurable FIR Filter Using BCSE Algorithm” has been selected for International conferences ISCON 2016 held on 7 – 8 January 2016, held at Karpagam University Coimbatore.

S.P.Prakash , Dr.S.Valarmathy , “Design and Analysis of Low power and Area efficient unsigned Array multiplier architecture “has been published in International Journal of Applied Engineering Research ISSN 0973-4562 Vol. 10, Number 14 (2015) pp 34352-3435. Annexure II

S.P.Prakash, Dr.S.Valarmathy, published a paper entitled “FPGA implementation of Address generator for IEEE 802.16E Deinterleaver using FSM” in National Conference on “Signals, Systems and Security” on 27 th and 28 th February 2014 at Bannari Amman Institute of Technology.

S.P.Prakash, Dr.S.Valarmathy, has published a paper entitled “Analysis of low power single precision floating point multiplier with rounding logic” in International Journal of Advanced Research in Computer Science and Software Engineering,ISSN:2277-128X 2014

S.P.Prakash, Dr.S.Valarmathy, has published a paper entitled “Implementation of floating point Adder units” in International Journal of Advanced Research in Electronics and Communication Engineering Vol. 3.Issue. 11 November 2014 pp1478 -1480.

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy, “An Efficient Decision Tree Based Architecture for Random Impulse Noice Removal in Image” International Journel of Advanced Research in Electrical Electronics and Instrumentation Engineering, Vol. 2, Issue 4, April 2013.

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy, “An efficient Hardware architecture based on DTBD Method for Random Impulse Noice Detection in Images” International Conference on Innovation in intelligent Instrumentation, Optimization and signal Processing (2013), Karunya University, Coimbatore. Page 1396 -1401.””

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy “ Design of Efficient Complementary pass Transistor based modified booth encoder array Multiplier” International journal of Computer application” Vol. 64 No. 5 February 2013

S.Sakthivel, S.P.Prakash,Dr.S.Valarmathy,” Design of Low power Parellel Multiplier with Column Bypassing Technique” 2 nd International conference on Innovative Research in Engineering and Technology, January 3 – 5, 2013.

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy, “ Design of an efficient Impulse Noise Detector Architecture using Decision Tree based Denoising method” Recent Advances in power Electronics and Industrial Drives (2013), INFO Institute of Engineering, Coimbator, PP 315-321

S.Saro Ramya, S.Sakthivel, S.P.Prakash “Design and comparison of Array and Tree multiplier using different logic style” International Journal of Innovative Technology, Vol. 2 Issue 7 January 2013.

S.P.Prakash,P.Saroramya, S.Sakthivel,” Design and Comparission of Low Power multipliers using different adder logic” 2 nd International conference on Innovative Research in Engineering and Technology, January 3 – 5, 2013.

Dr.S.Valarmathy, S.P.Prakash, S.Sakthivel “Design of low power parallel multiplier with column bypassing technique”, International Journal of Electrical Energy systems Vol. 5 No.1 January to June 2013 pp 41- 45

S.Sakthivel, S.P.Prakash, Dr.S.Valarmathy “ Design of adaptive reconfigurable FIR filter by using column bypassing Technique” International Journals of Inventive Engineering and Sciences, Vol. 6 No.2 July to December 2013 PP 44 – 50.

Lakshmi.C and Prakash.S.P, “Design and Analysis of Signed Array Multiplier Architecture for Low Power”, Proceedings of International Conference on Information Communication & Embedded System (ICICES – 2012),Feb 24 & 25 PP 69 – 75″”

Lakshmi.C and Prakash.S.P , “Design and Analysis of Signed Array Multiplier Architecture for Low Power” proceedings of National Conference on Telecommunication and Control Engineering (NCTCE 2012) 6 th January PP: 248-253″”

Prakash.S.P, Karthiga.T, “Design and Analysis of Low Power 3-2, 4-2 and 5-2 Compressor Architecture “, Proceedings of International Conferences on Futuristic Trends in Electronics Engineering (ICFTEE – 2012), January 28 &29 PP : 63-68″”

Lakshmi.C and Prakash.S.P, “Design and Analysis of Unsigned Array Multiplier Architecture for Low Power”, Proceedings of International Conference on Futuristic Trends in Computer Science Engineering & Information Technology (ICCT- 2012) January 28 &29 PP 86 – 90.””

S.P.Prakash, S.Saro Ramya and Dr.S.Valarmathy, “Design and Comparison of array and tree multiplier using different logic style”, Proc. of DRDO sponsored National Conference on Recent Trends in Control System and Power Electronics, 27-28 December 2012 held at Vivakanandha Institute of Engineering and Technology for Women Tiruchengode.””

Prakash.S.P, Dr.Valarmathy.S and Lakshmi.C, “Design and Analysis of Low power Braun Multiplier Architecture”, Indian Journal of Engineering Science, and Technology (IJEST), Vol.5 No.1, January – June 2011

Prakash S P,M.Abdullah , Kedir Behir, Abrah Ftsum Berhe, “Hybrid Frequency Domain Based Feature Extraction Methods for Human Face Recognition”, International Conference on “Smart Technologies, Communication And Robotics”, BIT, 2022.

Prakash S P,M.Abdullah , Kedir Behir, Abrah Ftsum Berhe, “Improved Local Vector Pattern Descriptor for Face Recognition”, International Conference On “Smart Technologies, Communication and Robotics”, BIT, 2022.

Prakash S P,S KARTHICK , “Gate Diffusion Input For Braun Multiplier”, International Virtual Conference on “Advanced Functional Material”, KL University, 2021.

M.Abdullah, Dr.K.Premalatha,S.P.Prakash, S.Kirubakaran, Dr. S.Karthick ,Dr.C.Kamalanathan, “Improved Local Vector Pattern for Face Recognition”, International Conference on Design Innovation, IEEE, Bangalore, May 2019

S.P.Prakash, Dr.R.S.Valarmathy, M.Abdullah, S.Kirubakaran, “Noval approach in Face recognition using Hieratical Multi Scale Local Binary Pattern with ELM Classifier”, International Conference on New Paradigms in Engineering Technology and Managemant -2017, Electronics Department, Pune, India., November 2017

S.P.Prakash, Dr.S.Valarmathy, “Constant Multiplier Architecture For Reconfigurable FIR Filter Using BCSE Algorithm”, International conferences ISCON 2016, ECE Department, Karpagam University Coimbatore., January 2016

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy, “Design of an efficient Impulse Noise Detector Architecture using Decision Tree based Denoising method”, Recent Advances in power Electronics and Industrial Drives , ECE Department, INFO Institute of Engineering, Coimbator, March 2013

Sajan P.P Philip, S.P.Prakash, Dr.S.Valarmathy, “An efficient Hardware architecture based on DTBD Method for Random Impulse Noice Detection in Images”, Innovation in intelligent Instrumentation, Optimization and signal Processing (2013), ECE Department, Karunya University, Coimbatore, January 2013

S.Sakthivel, S.P.Prakash,Dr.S.Valarmathy, “Design of Low power Parellel Multiplier with Column Bypassing Technique”, International conference on Innovative Research in Engineering and Technology, ECE Department, January 2013

S.P.Prakash,P.Saroramya, S.Sakthivel, “Design and Comparission of Low Power multipliers using different adder logic”, 2nd International conference on Innovative Research in Engineering and Technology, ECE Department, January 2013

S.P.Prakash, S.Saro Ramya and Dr.S.Valarmathy, “Design and Comparison of array and tree multiplier using different logic style”, National Conference on Recent Trends in Control System and Power Electronics, ECE Department, Vivakanandha Institute of Engineering and Technology for Women Tiruchengode. , December 2012

Design and Analysis of Signed Array Multiplier Architecture for Low Power, “Lakshmi.C and Prakash.S.P”, International Conference on Information Communication, ECE Department, February 2012

Lakshmi.C and Prakash.S.P, “Design and Analysis of Unsigned Array Multiplier Architecture for Low Power”, International Conference on Futuristic Trends in Computer Science Engineering , ECE Department, January 2012

Prakash.S.P, Karthiga.T, “Design and Analysis of Low Power 3-2, 4-2 and 5-2 Compressor Architecture”, International Conferences on Futuristic Trends in Electronics Engineering , ECE Department, January 2012

Lakshmi.C and Prakash.S.P , “Design and Analysis of Signed Array Multiplier Architecture for Low Power”, National Conference on Telecommunication and Control Engineering (NCTCE 2012), ECE Department, January 2011

S.No.	Title	Date	Reg. No.	Status	Level	Funding Agency
1	WIRELESS HEALTH-MONITORING SYSTEM	03.10.2023	396615-001	Filed	National	Self
2	AUTOMATED THEERTHAM SIDPERNSER (ATD)	29.09.2022	202241055882	Filed	National	Self
3	DISEASE ANALYSER - AI	20.08.2022	202241041494	Filed	National	Self
4	WOMAN SAFETY HIDDEN MALICIOUS CHIP USING IOT- BASED TRACKING TECHNOLOGY	04.07.2022	202241050744	Published	National	Self
5	VEHICLE THEFT DETECTION AND TRACKING SYSTEM	06.06.2022	202241032208	Filed	National	Self
6	PORTABLE MACHINE FOR GAS BURNER CLEANING	24.01.2022	202241003785	Filed	National	Self
7	A DEVICE TO ARREST TAP WATER LEAKAGE	09.08.2021	202141035801	Filed	National	Self